1. Wafer is created
The monocrystalline silicon ingot is sliced into wafers. Slurries are applied to polish the surface, then silicon oxide is grown on the surface in a thermal process.
2. Photoresist Coating applied
The wafers are rotated at high speed and coated with a thin, uniform photoresist film. Edge Bead Remover (EBR) is used to clean any buildup on the edge.
Yield Enhancers such as BARCs and TARCs are applied to minimise the light refraction and interference effects. The resist mask that contains the circuit pattern information is created.
4. Developing and Pattern Enhancement
The wafer is developed to remove the photoresist using aqueous developers. FIRM rinse is used to prevent line collapse. Pattern Enhancement processes (Relacs and line trimming) further improve the resist structures.
Varying photoresist patterns are applied through deposition of dielectrics, etching, or doping to form the active areas of the transistors, and to define the conductive connections.
The photoresist stages (2 to 4) are repeated between 30 to 50 times. Each time photoresist remnants are removed by strippers. To keep the chip surface flat, chemical mechanical polishing (CMP) is applied using slurries.
Single chip The finished chip is connected to the outside world by redistribution wiring and wafer bumping (solder or gold). These steps use thick film photoresists.
8. Bonding and Completion
Single chip The wafer is diced into individual chips, and bonded into a lead frame. The chips are encapsulated in a moulding material and encased in the final package.